In a recent study published by researchers from the Technical University of Darmstadt, a technical framework called “PQC-HA” is presented, which allows for the evaluation and prototyping of post-quantum cryptography hardware accelerators. The article, titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators,” focuses on optimizing software and hardware implementations of candidate schemes in the National Institute of Standards and Technology (NIST) post-quantum cryptography standardization project.
The study focuses on two winning schemes from the project, CRYSTALS Kyber and CRYSTALS Dilithium, which serve as Key Encapsulation Mechanism (KEM) and Digital Signature Algorithm (DSA) respectively. The researchers use the open-source framework TaPaSCo to create hardware building blocks for both schemes using high-level synthesis (HLS) from minimally modified ANSI C software reference implementations.
To verify the functionality of these hardware building blocks, a generic TaPaSCo runtime host application is developed in Rust. The application utilizes the NIST standard interface and the corresponding known-answer test mechanism to evaluate the performance of the hardware accelerators on real hardware. This approach allows for the verification and evaluation of post-quantum cryptography accelerators on real hardware.
Additionally, the study evaluates the communication overhead of TaPaSCo hardware accelerators on FPGA devices connected to PCIe and compares it with previous works and optimized software reference implementations using AVX2. The results highlight the feasibility of using TaPaSCo to evaluate the performance of post-quantum cryptography accelerators on real hardware.
The study also measures the off-chip communication overhead of the accelerator from the NIST standard interface. Interestingly, this overhead alone surpasses the real-time execution of the optimized software reference implementation of Kyber at Security Level 1.
In summary, this research article provides valuable insights into the prototyping and in-hardware evaluation of post-quantum cryptography hardware accelerators. It demonstrates the feasibility of using TaPaSCo to verify and evaluate the performance of these accelerators on real hardware. These findings contribute to the ongoing efforts of the NIST post-quantum cryptography standardization project and pave the way for future advancements in secure cryptographic systems.
Source: Sattel, Richard, Christoph Spang, Carsten Heinz, and Andreas Koch. “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators”. arXiv preprint arXiv:2308.06621 (2023).